`include "defines.v"
module mem_wb(
	input wire clk,
	input wire rst,
	input wire[31:0] write_data_i,
	input wire write_ce_i,
	input wire[4:0] write_addr_i,
	output reg[31:0] write_data_o,
	output reg write_ce_o,
	output reg[4:0] write_addr_o,
	
	//与hilo寄存器相关的数据
	input wire[31:0] hi_i,
	input wire[31:0] lo_i,
	input wire hilo_write_ce_i,
	output reg[31:0] hi_o,
	output reg[31:0] lo_o,
	output reg hilo_write_ce_o,
	input wire[5:0] pause, //流水线暂停信号
	//ll,sc指令相关信号
	input wire LLbit_wCe_i,
	input wire LLbit_wData_i,
	output reg LLbit_wCe_o,
	output reg LLbit_wData_o,
	//异常相关
	input wire exception,
	//CP0相关信号
	input wire[31:0] cp0_wData_i,
	input wire[4:0] cp0_wAddr_i,
	input wire cp0_wCe_i,
	output reg[31:0] cp0_wData_o,
	output reg[4:0] cp0_wAddr_o,
	output reg cp0_wCe_o
	
);
	always@(posedge clk)
		if(rst == `RstEnable)
		begin
			write_data_o <= `ZeroWord;
			write_ce_o <= `WriteDisable;
 			write_addr_o <= 5'b00000;
			hi_o <= `ZeroWord;
			lo_o <= `ZeroWord;
			hilo_write_ce_o <= `WriteDisable;
			
			LLbit_wCe_o <= 1'b0;
			LLbit_wData_o <= 1'b0;
			
			cp0_wData_o = `ZeroWord;
			cp0_wAddr_o = 5'b00000;
			cp0_wCe_o = `WriteDisable;
		end
		else if((exception == `Exception_Happen) || (pause[4] == `PAUSE && pause[5] == `NO_PAUSE)) //访存阶段暂停，回写阶段继续
		begin
			write_data_o <= `ZeroWord;
			write_ce_o <= `WriteDisable;
 			write_addr_o <= 5'b00000;
			hi_o <= `ZeroWord;
			lo_o <= `ZeroWord;
			hilo_write_ce_o <= `WriteDisable;
			
			LLbit_wCe_o <= 1'b0;
			LLbit_wData_o <= 1'b0;
			
			cp0_wData_o = `ZeroWord;
			cp0_wAddr_o = 5'b00000;
			cp0_wCe_o = `WriteDisable;
		end
		else if(pause[4] == `NO_PAUSE)
		begin
			write_data_o <= write_data_i;
			write_ce_o <= write_ce_i; 
			write_addr_o <= write_addr_i;
			hi_o <= hi_i;
			lo_o <= lo_i;
			hilo_write_ce_o <= hilo_write_ce_i;
			
			LLbit_wCe_o <= LLbit_wCe_i;
			LLbit_wData_o <= LLbit_wData_i;
			
			cp0_wData_o = cp0_wData_i;
			cp0_wAddr_o = cp0_wAddr_i;
			cp0_wCe_o = cp0_wCe_i;
		end
endmodule
